Speakers

Abstract

FET100 - Plennary Talks - Evolution of CMOS from the Invention toward Nowadays 3D CMOS for AI

The concept of the field-effect transistor (FET) was proposed in 1925 as an amplifier for telecommunication that controlled the current in a Cu₂S thin film using a metal gate. In 1928, a MOSFET structure with a gate-oxide insulator was invented, but the quality of semiconductor thin films at the time was too poor for practical operation. Achieving functional MOSFETs required the establishment of numerous principles and technologies, including high-purity silicon, single-crystal substrates, the discovery of the inversion layer, the pn junction, thermal SiO₂, doping techniques, and photolithography. With these advances in place, MOSFET operation was finally demonstrated in 1960.

In the late 1960s, MOSFET-based SSI/MSI began, but instability caused by surface charges limited market adoption. Large-scale use started only in the last year of the 1960s and into the early 1970s, when MOS devices were employed in diverse LSI applications such as calculator logic, DRAM/SRAM, and microprocessors. Early LSIs had minimum feature sizes of 10–8 µm, but n-MOSFETs suffered from positive charges at the Si/SiO₂ interface that drove the threshold voltage negative, preventing transistors from turning off; therefore, p-MOSFETs were used. With the commercialization of ion-implantation machines in the 1970s, threshold control for n-MOS became possible, and high-mobility NMOS LSIs became mainstream from the 6-µm generation onward. Thereafter, scaling progressed every two to three years, enabling continuous increases in integration density and performance.

By the mid-1980s, at the 1-µm generation, power consumption and heat dissipation reached critical limits, making CMOS — where p-MOSFETs and n-MOSFETs are connected in series to suppress through-current — an essential technology. Although CMOS had been invented in 1963 and adopted in low-power devices in the late 1960s, its well structures and manufacturing complexity limited early adoption. From the mid-1980s onward, however, CMOS became the standard technology for LSI.

Since 1960, MOSFET channels have been formed using inversion layers on silicon single-crystal surfaces. Early FET patents envisioned controlling the entire thin film with the gate field, but this required high-quality films as thin as molecular dimensions, which were not achievable for decades. As a result, MOSFETs using inversion layers on bulk single-crystal substrates — i.e., bulk MOSFETs — remained the only practical option for high-performance LSIs.

When gate lengths shrank to a few tens of nanometers, the drain electric field raised the substrate potential near the source, causing threshold-voltage reduction and punch-through currents. To strongly control the channel potential near the source, double-gate (DG) structures with gate electrodes above and below the silicon thin film were investigated. Manufacturing of FinFET LSIs — a type of DG structure — began at the 22-nm generation in 2012, and FinFETs became the mainstream technology for leading-edge LSIs. Although DG concepts had been proposed since 1935, experimental FinFET operation was first demonstrated in 1989, and its introduction into products took more than 30 years.

As gate lengths approached 10 nm, even stronger electrostatic control became necessary. Gate-All-Around (GAA) structures, in which the gate electrode surrounds silicon nanosheets only a few nanometers thick, began to be used in parts of the 3-nm generation starting in 2024. From the 2-nm generation onward, manufacturers have adopted three-dimensional GAA integration, stacking multiple nanosheet channels vertically. GAA also has a long history, with the concept proposed in 1957 and experimental demonstration in 1986.

GAA 3D-integrated LSIs have extremely complex structures and require many fabrication steps, resulting in enormous manufacturing costs. However, the strong demand for AI has supported the production of these high-cost LSIs.

The scaling of gate length and minimum feature size is expected to reach its limit around 10 nm, and current LSI development is shifting toward three-dimensional integration. Increasing process complexity, rising costs, declining yield, and higher heat generation per unit area due to 3D integration are becoming major challenges.

This talk will explain the evolution of LSI technology, discuss current issues, and address future prospects.

Biography

Hiroshi Iwai received his B.E. and Ph.D. degrees from the University of Tokyo. After joining Toshiba in 1973, he devoted more than fifty years to advancing LSI technologies and products, from the 8-µm PMOS LSI generation to the present, through his work at Toshiba, the Tokyo Institute of Technology / Institute of Science Tokyo, and NCTU / NYCU. His wide-ranging contributions include developing Toshiba's first NMOS LSI technology and 1-kbit SRAM in the mid-1970s, which was later used in the world's first microprocessor-based engine control system for the 1978 Ford Lincoln Versailles. In the late 1970s, he introduced stepper lithography and dry processes for 64k DRAM mass production, achieving one of the earliest VLSI fabrication approaches worldwide.

In the early 1990s, he operated sub-50 nm MOSFETs — two generations ahead of competitors — and developed essential sub-50 nm technologies such as NiSi salicide, presenting a roadmap down to sub-25 nm. In the mid-1990s, he launched Toshiba's RF CMOS project, realized a one-chip RF front-end for GSM with European collaborators, and established the RF CMOS roadmap that underpins modern smartphones.

He has received major awards including the IEEE EDS J.J. Ebers Award, Paul Rappoport Award, Cledo Brunetti Award, ECS Callinan Award, and ECS Gordon Moore Medal. He is a Life Fellow of IEEE, ECS, and JSAP, and a Fellow of IEICE and IEE Japan. He is an Eminent Lecturer at IEEE EDS. He served as IEEE EDS President (2004–05) and IEEE Division I Director (2010–11). He currently serves as Vice Dean and Distinguished Chair Professor at NYCU and as Professor Emeritus at the Institute of Science Tokyo.